Computer-aided dispatch system family architecture and verification: An integrated formal approach

10.1049/ip-sen:20050014

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Main Authors: Sun, J., Dong, J.S., Jarzabek, S., Wang, H.
Other Authors: COMPUTER SCIENCE
Format: Article
Published: 2013
Online Access:http://scholarbank.nus.edu.sg/handle/10635/38941
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Institution: National University of Singapore
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spelling sg-nus-scholar.10635-389412023-10-30T07:04:23Z Computer-aided dispatch system family architecture and verification: An integrated formal approach Sun, J. Dong, J.S. Jarzabek, S. Wang, H. COMPUTER SCIENCE 10.1049/ip-sen:20050014 IEE Proceedings: Software 153 3 102-112 IPSEF 2013-07-04T07:30:22Z 2013-07-04T07:30:22Z 2006 Article Sun, J., Dong, J.S., Jarzabek, S., Wang, H. (2006). Computer-aided dispatch system family architecture and verification: An integrated formal approach. IEE Proceedings: Software 153 (3) : 102-112. ScholarBank@NUS Repository. https://doi.org/10.1049/ip-sen:20050014 14625970 http://scholarbank.nus.edu.sg/handle/10635/38941 000239099300002 Scopus
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
description 10.1049/ip-sen:20050014
author2 COMPUTER SCIENCE
author_facet COMPUTER SCIENCE
Sun, J.
Dong, J.S.
Jarzabek, S.
Wang, H.
format Article
author Sun, J.
Dong, J.S.
Jarzabek, S.
Wang, H.
spellingShingle Sun, J.
Dong, J.S.
Jarzabek, S.
Wang, H.
Computer-aided dispatch system family architecture and verification: An integrated formal approach
author_sort Sun, J.
title Computer-aided dispatch system family architecture and verification: An integrated formal approach
title_short Computer-aided dispatch system family architecture and verification: An integrated formal approach
title_full Computer-aided dispatch system family architecture and verification: An integrated formal approach
title_fullStr Computer-aided dispatch system family architecture and verification: An integrated formal approach
title_full_unstemmed Computer-aided dispatch system family architecture and verification: An integrated formal approach
title_sort computer-aided dispatch system family architecture and verification: an integrated formal approach
publishDate 2013
url http://scholarbank.nus.edu.sg/handle/10635/38941
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