Verifying stateful timed CSP using implicit clocks and zone abstraction
10.1007/978-3-642-10373-5_30
Saved in:
Main Authors: | Sun, J., Liu, Y., Dong, J.S., Zhang, X. |
---|---|
Other Authors: | COMPUTER SCIENCE |
Format: | Conference or Workshop Item |
Published: |
2013
|
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/40018 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Verifying stateful timed CSP using implicit clocks and zone abstraction
by: SUN, Jun, et al.
Published: (2009) -
Modeling and verifying hierarchical real-time systems using stateful timed CSP
by: Sun, J., et al.
Published: (2013) -
Modeling and verifying hierarchical real-time systems using stateful timed CSP
by: SUN, Jun, et al.
Published: (2013) -
Improving model checking stateful timed CSP with non-zenoness through clock-symmetry reduction
by: SI, Yuanjie, et al.
Published: (2013) -
Symbolic model-checking of stateful timed CSP using BDD and digitization
by: Nguyen, T.K., et al.
Published: (2013)