Analysis and design of power factor correction using half bridge boost topology

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

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Bibliographic Details
Main Authors:	Srinivasan, Ramesh, Oruganti, Ramesh
Other Authors:	ELECTRICAL ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/72480
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-72480
record_format	dspace
spelling	sg-nus-scholar.10635-724802015-02-07T17:03:46Z Analysis and design of power factor correction using half bridge boost topology Srinivasan, Ramesh Oruganti, Ramesh ELECTRICAL ENGINEERING Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC 1 489-499 CPAEE 2014-06-19T05:08:32Z 2014-06-19T05:08:32Z 1997 Conference Paper Srinivasan, Ramesh,Oruganti, Ramesh (1997). Analysis and design of power factor correction using half bridge boost topology. Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC 1 : 489-499. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/72480 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
author2	ELECTRICAL ENGINEERING
author_facet	ELECTRICAL ENGINEERING Srinivasan, Ramesh Oruganti, Ramesh
format	Conference or Workshop Item
author	Srinivasan, Ramesh Oruganti, Ramesh
spellingShingle	Srinivasan, Ramesh Oruganti, Ramesh Analysis and design of power factor correction using half bridge boost topology
author_sort	Srinivasan, Ramesh
title	Analysis and design of power factor correction using half bridge boost topology
title_short	Analysis and design of power factor correction using half bridge boost topology
title_full	Analysis and design of power factor correction using half bridge boost topology
title_fullStr	Analysis and design of power factor correction using half bridge boost topology
title_full_unstemmed	Analysis and design of power factor correction using half bridge boost topology
title_sort	analysis and design of power factor correction using half bridge boost topology
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/72480
_version_	1681087573559083008

Analysis and design of power factor correction using half bridge boost topology

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