Single phase parallel power processing scheme with input-shunt power factor correction stage

Proceedings of the International Conference on Power Electronics and Drive Systems

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Bibliographic Details
Main Authors:	Srinivasan, Ramesh, Oruganti, Ramesh
Other Authors:	ELECTRICAL ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/81751
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-81751
record_format	dspace
spelling	sg-nus-scholar.10635-817512015-12-12T23:22:40Z Single phase parallel power processing scheme with input-shunt power factor correction stage Srinivasan, Ramesh Oruganti, Ramesh ELECTRICAL ENGINEERING Proceedings of the International Conference on Power Electronics and Drive Systems 2 611-620 85RTA 2014-10-07T03:11:37Z 2014-10-07T03:11:37Z 1997 Conference Paper Srinivasan, Ramesh,Oruganti, Ramesh (1997). Single phase parallel power processing scheme with input-shunt power factor correction stage. Proceedings of the International Conference on Power Electronics and Drive Systems 2 : 611-620. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/81751 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	Proceedings of the International Conference on Power Electronics and Drive Systems
author2	ELECTRICAL ENGINEERING
author_facet	ELECTRICAL ENGINEERING Srinivasan, Ramesh Oruganti, Ramesh
format	Conference or Workshop Item
author	Srinivasan, Ramesh Oruganti, Ramesh
spellingShingle	Srinivasan, Ramesh Oruganti, Ramesh Single phase parallel power processing scheme with input-shunt power factor correction stage
author_sort	Srinivasan, Ramesh
title	Single phase parallel power processing scheme with input-shunt power factor correction stage
title_short	Single phase parallel power processing scheme with input-shunt power factor correction stage
title_full	Single phase parallel power processing scheme with input-shunt power factor correction stage
title_fullStr	Single phase parallel power processing scheme with input-shunt power factor correction stage
title_full_unstemmed	Single phase parallel power processing scheme with input-shunt power factor correction stage
title_sort	single phase parallel power processing scheme with input-shunt power factor correction stage
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/81751
_version_	1681089128216657920

Single phase parallel power processing scheme with input-shunt power factor correction stage

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