An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Desig...

by Anwer, Janhanzeb, Hamid, Nor Hisham, Asirvadam , Vijanth Sagayan
Published 2011

Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

by Anwer, Janhanzeb, Khalid, Usman, Hamid, Nor Hisham, Asirvadam , Vijanth Sagayan
Published 2010

Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

by Anwer, Janhanzeb, Khalid, Usman, Hamid, Nor Hisham, Asirvadam , Vijanth Sagayan, Singh, Narenderjit
Published 2010