Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decre...

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Bibliographic Details
Main Authors: Anwer, Janhanzeb, Khalid, Usman, Hamid, Nor Hisham, Asirvadam , Vijanth Sagayan
Format: Conference or Workshop Item
Published: 2010
Subjects:
Online Access:http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5479997&tag=1
http://eprints.utp.edu.my/4072/
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Institution: Universiti Teknologi Petronas