Modified short-run statistical process control for test and measurement process

by Koh, C.K., Chin, J.F., Kamaruddin, S.
Published 2019

Modified SPC for short run test and measurement process in multi-stations

by Koh, C.K., Chin, J.F., Kamaruddin, S.
Published 2018

Modified short-run statistical process control for test and measurement process

by Koh, C.K., Chin, J.F., Kamaruddin, S.
Published 2019

Structured Use of External Knowledge for Event-based Open Domain Question Answering

by Yang, H., Chua, T.-S., Wang, S., Koh, C.-K.
Published 2013

A performance and power co-optimization approach for modern processors

by Zhu, Y., Wong, W.-F., Koh, C.-K.
Published 2013

Processor caches built using multi-level spin-transfer torque RAM cells

by Chen, Y., Wong, W.-F., Li, H., Koh, C.-K.
Published 2013

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

by Koh, C.-K., Wong, W.-F., Chen, Y., Li, H.
Published 2013

Tolerating process variations in large, set-associative caches: The buddy cache

by Koh, C.-K., Wong, W.-F., Chen, Y., Li, H.
Published 2013

Relationship between fern development and CAM in Pyrrosia piloselloides (L.) Price

by Ong, B.-L., Koh, C.K.-K., Wee, Y.-C.
Published 2014

Effects of CO2 on growth and photosynthesis of Pyrrosia piloselloides (L.) price gametophytes

by Ong, B.-L., Koh, C.K.-K., Wee, Y.-C.
Published 2014

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

by Chen, Y., Wong, W.-F., Li, H., Koh, C.-K., Zhang, Y., Wen, W.
Published 2014

Multidrug-resistant tuberculosis outbreak in gaming centers, Singapore, 2012

by Chee, C.B.E, Gan, S.-H, Ong, R.T, Sng, L.-H, Wong, C.W, Cutter, J, Gong, M, Seah, H.-M, Hsu, L.Y, Solhan, S, Ooi, P.-L, Xia, E, Lim, J.T, Koh, C.-K, Lim, S.-K, Lim, H.-K, Wang, Y.-T
Published 2020