On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

10.1145/2463585.2463592

Saved in:
Bibliographic Details
Main Authors: Chen, Y., Wong, W.-F., Li, H., Koh, C.-K., Zhang, Y., Wen, W.
Other Authors: COMPUTER SCIENCE
Format: Article
Published: 2014
Subjects:
Cache
Memories
MLC
Spintronic
STT-RAM
Online Access:http://scholarbank.nus.edu.sg/handle/10635/77896
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: National University of Singapore

Internet

http://scholarbank.nus.edu.sg/handle/10635/77896

Similar Items