On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

10.1145/2463585.2463592

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Bibliographic Details
Main Authors: Chen, Y., Wong, W.-F., Li, H., Koh, C.-K., Zhang, Y., Wen, W.
Other Authors: COMPUTER SCIENCE
Format: Article
Published: 2014
Subjects:
Cache
Memories
MLC
Spintronic
STT-RAM
Online Access:http://scholarbank.nus.edu.sg/handle/10635/77896
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Institution: National University of Singapore
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spelling sg-nus-scholar.10635-778962024-11-13T03:28:48Z On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations Chen, Y. Wong, W.-F. Li, H. Koh, C.-K. Zhang, Y. Wen, W. COMPUTER SCIENCE Cache Memories MLC Spintronic STT-RAM 10.1145/2463585.2463592 ACM Journal on Emerging Technologies in Computing Systems 9 2 - 2014-07-04T03:10:04Z 2014-07-04T03:10:04Z 2013 Article Chen, Y., Wong, W.-F., Li, H., Koh, C.-K., Zhang, Y., Wen, W. (2013). On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM Journal on Emerging Technologies in Computing Systems 9 (2) : -. ScholarBank@NUS Repository. https://doi.org/10.1145/2463585.2463592 15504832 http://scholarbank.nus.edu.sg/handle/10635/77896 000323705000007 Scopus
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
topic Cache
Memories
MLC
Spintronic
STT-RAM
spellingShingle Cache
Memories
MLC
Spintronic
STT-RAM
Chen, Y.
Wong, W.-F.
Li, H.
Koh, C.-K.
Zhang, Y.
Wen, W.
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
description 10.1145/2463585.2463592
author2 COMPUTER SCIENCE
author_facet COMPUTER SCIENCE
Chen, Y.
Wong, W.-F.
Li, H.
Koh, C.-K.
Zhang, Y.
Wen, W.
format Article
author Chen, Y.
Wong, W.-F.
Li, H.
Koh, C.-K.
Zhang, Y.
Wen, W.
author_sort Chen, Y.
title On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
title_short On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
title_full On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
title_fullStr On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
title_full_unstemmed On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
title_sort on-chip caches built on multilevel spin-transfer torque ram cells and its optimizations
publishDate 2014
url http://scholarbank.nus.edu.sg/handle/10635/77896
_version_ 1821184808171077632

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