On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
10.1145/2463585.2463592
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| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Article |
| Published: |
2014
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| Subjects: | |
| Online Access: | http://scholarbank.nus.edu.sg/handle/10635/77896 |
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| Institution: | National University of Singapore |