A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

by Rofail, Samir S., Yeo, Kiat Seng
Published 2009

Experimentally-based analytical model of deep-submicron LDD pMOSFET’s in a Bi-MOS hybrid-mode environment

by Rofail, Samir S., Yeo, Kiat Seng
Published 2009

A low-power 16×16-b parallel multiplier utilizing pass-transistor logic

by Law, C. F., Rofail, Samir S., Yeo, Kiat Seng
Published 2009

A temperature-dependent DC model for quarter-micron LDD pMOSFET’s operating in a Bi-MOS structure

by Rofail, Samir S., Chew, Kok Wai Johnny, Yeo, Kiat Seng
Published 2009

Basic logic circuits and arithmetic subsystems for low-power applications

by Law, Chong Fatt.
Published 2008

Analytical and experimental characterization of sub-half micron MOS devices

by Chew, Johnny Kok Wai.
Published 2008