A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

• Main Authors: Rofail, Samir S., Yeo, Kiat Seng
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2009
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/91615; http://hdl.handle.net/10220/6007
• 機構: Nanyang Technological University

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reporte...