A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reporte...

Full description

Saved in:

Bibliographic Details
Main Authors:	Rofail, Samir S., Yeo, Kiat Seng
Other Authors:	School of Electrical and Electronic Engineering
Format:	Article
Language:	English
Published:	2009
Subjects:	DRNTU::Engineering::Electrical and electronic engineering
Online Access:	https://hdl.handle.net/10356/91615 http://hdl.handle.net/10220/6007
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-91615
record_format	dspace
spelling	sg-ntu-dr.10356-916152020-03-07T14:02:41Z A charge-trapping-based technique to design low-voltage BiCMOS logic circuits Rofail, Samir S. Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-µm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates. Published version 2009-08-03T04:29:03Z 2019-12-06T18:08:58Z 2009-08-03T04:29:03Z 2019-12-06T18:08:58Z 1998 1998 Journal Article Yeo, K. S., & Samir, S. R. (1998). A charge-trapping-based technique to design low-voltage BiCMOS logic circuits. IEEE Journal of Solid-State Circuits, 33(1), 164-168. 0018-9200 https://hdl.handle.net/10356/91615 http://hdl.handle.net/10220/6007 10.1109/4.654950 en IEEE journal of solid-state circuits IEEE Journal of Solid-State Circuits © 1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site. 5 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering Rofail, Samir S. Yeo, Kiat Seng A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
description	New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-µm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Rofail, Samir S. Yeo, Kiat Seng
format	Article
author	Rofail, Samir S. Yeo, Kiat Seng
author_sort	Rofail, Samir S.
title	A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
title_short	A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
title_full	A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
title_fullStr	A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
title_full_unstemmed	A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
title_sort	charge-trapping-based technique to design low-voltage bicmos logic circuits
publishDate	2009
url	https://hdl.handle.net/10356/91615 http://hdl.handle.net/10220/6007
_version_	1681034898815582208

A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

Similar Items