A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reporte...
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| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/91615 http://hdl.handle.net/10220/6007 |
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| Institution: | Nanyang Technological University |
| Language: | English |