CMOS differential logic circuits for low power and high-speed applications
A new CSDL circuit is proposed which reduces the number of transistors and input signals required compared to the original CSDL circuit.
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/3586 |
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| Institution: | Nanyang Technological University |