CMOS differential logic circuits for low power and high-speed applications
A new CSDL circuit is proposed which reduces the number of transistors and input signals required compared to the original CSDL circuit.
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2008
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sg-ntu-dr.10356-35862023-07-04T15:18:56Z CMOS differential logic circuits for low power and high-speed applications They, Kian Seng Lau, Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits A new CSDL circuit is proposed which reduces the number of transistors and input signals required compared to the original CSDL circuit. Master of Science (Integrated Circuit Design) 2008-09-17T09:33:00Z 2008-09-17T09:33:00Z 2004 2004 Thesis http://hdl.handle.net/10356/3586 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits They, Kian Seng CMOS differential logic circuits for low power and high-speed applications |
description |
A new CSDL circuit is proposed which reduces the number of transistors and input signals required compared to the original CSDL circuit. |
author2 |
Lau, Kim Teen |
author_facet |
Lau, Kim Teen They, Kian Seng |
format |
Theses and Dissertations |
author |
They, Kian Seng |
author_sort |
They, Kian Seng |
title |
CMOS differential logic circuits for low power and high-speed applications |
title_short |
CMOS differential logic circuits for low power and high-speed applications |
title_full |
CMOS differential logic circuits for low power and high-speed applications |
title_fullStr |
CMOS differential logic circuits for low power and high-speed applications |
title_full_unstemmed |
CMOS differential logic circuits for low power and high-speed applications |
title_sort |
cmos differential logic circuits for low power and high-speed applications |
publishDate |
2008 |
url |
http://hdl.handle.net/10356/3586 |
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1772826399089885184 |