Low power CMOS circuits

• Main Author: Teo, Kok Chin
• Other Authors: Lau Kim Teen
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/61400
• Institution: Nanyang Technological University

Basic building block of CMOS integrated circuit like inverter, NAND, Latch and Full Adder will be simulated under low voltage condition using the Cadence software. This is an attempt to study the operations of these circuits when voltage is lowered to reduce the power consumption. Results will then...