Low power CMOS circuits
Basic building block of CMOS integrated circuit like inverter, NAND, Latch and Full Adder will be simulated under low voltage condition using the Cadence software. This is an attempt to study the operations of these circuits when voltage is lowered to reduce the power consumption. Results will then...
Saved in:
Main Author: | Teo, Kok Chin |
---|---|
Other Authors: | Lau Kim Teen |
Format: | Final Year Project |
Language: | English |
Published: |
2014
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/61400 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Low power CMOS memory circuit design
by: Foo, Chee Heng
Published: (2020) -
CMOS differential logic circuits for low power and high-speed applications
by: They, Kian Seng
Published: (2008) -
Low voltage low power CMOS circuits for IoT applications
by: Liu, Yue
Published: (2019) -
Analysis of CMOS circuits : glitch power
by: Cai, Hong
Published: (2008) -
Circuit performance sensitivity analysis of CMOS low noise amplifiers
by: Lim, Eng Chun.
Published: (2008)