Comparison of low power CMOS dynamic circuit design

• Main Author: A Sadhananthan, Karthikeyan
• Other Authors: Lau Kim Teen
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/61506
• Institution: Nanyang Technological University

The bulk of the power consumption for conventional CMOS dynamic logic is usually contributed as a result of the clock signal constantly changing. While this does not consume much power at low frequencies, it becomes a major issue at much higher frequencies. Therefore for low power, high spe...