Comparison of low power CMOS dynamic circuit design

• Main Author: A Sadhananthan, Karthikeyan
• Other Authors: Lau Kim Teen
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/61506
• Institution: Nanyang Technological University

The bulk of the power consumption for conventional CMOS dynamic logic is usually contributed as a result of the clock signal constantly changing. While this does not consume much power at low frequencies, it becomes a major issue at much higher frequencies. Therefore for low power, high speed circuit applications there have been extensive research conducted over the past years to look into methods which would replace the clock signal of the circuit while still maintain its dynamic nature. This resulted in various low power circuit logics which are suitable for replacing the conventional dynamic logic. These include Domino logic, NP-CMOS logic, Data- Driven Dynamic Logic(D3L),Differential Cascode Voltage Swing Logic (DCVSL), Dual-Rail Data-Driven Dynamic Logic(D4L). While most of these low power design techniques have been compared with the conventional Dynamic logic and assessed based on their performance, there have been no research conducted in evaluating the performance based on a comparison of all of the low power circuit design techniques with each other. This project serves to look into the performance of each type of low power circuit design techniques with regards to circuit area, delay, accuracy of result and power consumption. A 28 transistor full adder is used as the basic circuit for this project. The above 5 mentioned low power circuit design techniques will be used to implement this 28 transistor full adder and the various performance parameters will be recorded accordingly. The power of the circuit will be the average power recorded. The circuit area will be calculated using the number of transistors which are used. While this is not an accurate measure it does serve as a general guideline. The delay of the circuit will be measured from the difference in the time taken for Cout to change after Cin changes value. In addition to this, a hybrid circuit of the D3L logic and NPCMOS logic will be designed and its performance parameters will be evaluated as well to see if this actually makes an improvement to the existing circuit design technique