CMOS differential logic circuits for low power and high-speed applications
A new CSDL circuit is proposed which reduces the number of transistors and input signals required compared to the original CSDL circuit.
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Theses and Dissertations |
| Published: |
2008
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/3586 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Summary: | A new CSDL circuit is proposed which reduces the number of transistors and input signals required compared to the original CSDL circuit. |
|---|