Design and optimization of a low-voltage CMOS circuit for portable applications

• Main Author: Chan, Chee Chong.
• Other Authors: Yeo, Kiat Seng
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/3116
• Institution: Nanyang Technological University

In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by...