Design and optimization of a low-voltage CMOS circuit for portable applications

Design and optimization of a low-voltage CMOS circuit for portable applications

In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by...

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Main Author: Chan, Chee Chong.
Other Authors: Yeo, Kiat Seng
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:http://hdl.handle.net/10356/3116
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Institution: Nanyang Technological University
id sg-ntu-dr.10356-3116
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spelling sg-ntu-dr.10356-31162023-07-04T15:18:16Z Design and optimization of a low-voltage CMOS circuit for portable applications Chan, Chee Chong. Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by replacing the dual ripple-carry adders with a carry skip adder for zero-carry in. Master of Science (Integrated Circuit Design) 2008-09-17T09:22:36Z 2008-09-17T09:22:36Z 2003 2003 Thesis http://hdl.handle.net/10356/3116 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Chan, Chee Chong.
Design and optimization of a low-voltage CMOS circuit for portable applications
description In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by replacing the dual ripple-carry adders with a carry skip adder for zero-carry in.
author2 Yeo, Kiat Seng
author_facet Yeo, Kiat Seng
Chan, Chee Chong.
format Theses and Dissertations
author Chan, Chee Chong.
author_sort Chan, Chee Chong.
title Design and optimization of a low-voltage CMOS circuit for portable applications
title_short Design and optimization of a low-voltage CMOS circuit for portable applications
title_full Design and optimization of a low-voltage CMOS circuit for portable applications
title_fullStr Design and optimization of a low-voltage CMOS circuit for portable applications
title_full_unstemmed Design and optimization of a low-voltage CMOS circuit for portable applications
title_sort design and optimization of a low-voltage cmos circuit for portable applications
publishDate 2008
url http://hdl.handle.net/10356/3116
_version_ 1772826458445578240

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