Design and optimization of a low-voltage CMOS circuit for portable applications

In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by...

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Bibliographic Details
Main Author: Chan, Chee Chong.
Other Authors: Yeo, Kiat Seng
Format: Theses and Dissertations
Published: 2008
Subjects:
Online Access:http://hdl.handle.net/10356/3116
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Institution: Nanyang Technological University

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