Programmable cyclic redundancy check encoder/decoder with VLSI implementation.

by Yap, Roderick Y.
Published 1993

Hardware modeling development of a convolutional neural network with K-means-clustered weights in rapid prototyping systems: Advances and limitations

by Yap, Roderick Y.
Published 2019

A guide to HDL modeling of a non-pipelined central processing unit design

by Yap, Roderick Y.
Published 2002

Design, development and implementation of a fuzzy logic controller for DC-DC buck and boost converter in an FPGA

by Caldo, Rionel Belen, Yap, Roderick Y.
Published 2013

Design and development of audit central data bank at Ibiden Philippines, Inc. (IPI)

by Caldo, Rionel Belen, Yap, Roderick Y.
Published 2012

Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter

by Abad, Alexander C., Yap, Roderick Y.
Published 2011