Programmable cyclic redundancy check encoder/decoder with VLSI implementation.

Programmable cyclic redundancy check encoder/decoder with VLSI implementation.

ABSTRACT see Upload (MT ENGRNG 43 1993)

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Bibliographic Details
Main Author: Yap, Roderick Y.
Format: Theses and Dissertations NonPeerReviewed
Published: 1993
Subjects:
T Technology (General)
Online Access:http://thesis.dlsud.edu.ph/3943/1/Programmable%20cyclic...%20-%20Roderick%20Yap.pdf
http://thesis.dlsud.edu.ph/3943/2/MT%20ENGRNG%2043.pdf
http://thesis.dlsud.edu.ph/3943/
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Institution: De La Salle University

Internet

http://thesis.dlsud.edu.ph/3943/1/Programmable%20cyclic...%20-%20Roderick%20Yap.pdf
http://thesis.dlsud.edu.ph/3943/2/MT%20ENGRNG%2043.pdf
http://thesis.dlsud.edu.ph/3943/

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