BACK END DESIGN FOR DVB-T BASEBAND CHIP

• Main Author: FAJAR FIRDAUS (NIM : 13205033), AHMAD
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/13216
• Institution: Institut Teknologi Bandung

DVB-T, stand of Digital Video Broadcasting-Terrestrial is the next television system in Indonesia. This technology was developed based on ETSI (European Telecommunication <br /> <br /> <br /> <br /> <br /> <br /> Standards Institute) standard. One of hardware implementation of DVB-T technology is baseband chip receiver. This kind of implementation will through several steps i.e. modeling matlab, circuit design by using HDL, and backend design. Backend design covers code rule check, synthesis, formality, ATPG, floorplanning, placement&routing, and design rule check. In this final project research, writer did backend design steps partially. The steps are code rule check, synthesis, floorplanning, placement&routing, and design rule check. The steps were processed by using a serial of Synopsys® softwares. In synthesis step, scripts were made to describe synthesis environment and synthesis constraint based on specification. In the floorplanning, several scripts were made based on proposed floorplanning design flow and floorplanning planning that will be processed by placement&routing. As floorplanning, in the placement&routing there are some scripts were created based on proposed placement&routing design flow. The final result of these backend steps is a chip layout <br /> <br /> <br /> <br /> <br /> <br /> which is verified by design rule check that created by the foundry. The layouted chip has slack setup time 5.00 ns and slack hold time 0.02 ns. The chip has core utilization 83.45 %, core size 2029.98 um x 2029.50 um, and chip size 20670 um x 2670 um. This final project report presents a documentary of the project, also providing conclusion of the project.