DESIGN OF ASYNCHRONOUS PIPELINE EMPLOYING 2-PHASE AND 4-PHASE BUNDLED-DATA PUSH-CHANNEL IN VHDL

• Main Author: ISA MARTINUS (NIM : 23207033); Pembimbing : Ir. Yudi Satria Gondokaryono, MSEE, Ph.D., AGUST
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/14728
• Institution: Institut Teknologi Bandung

A digital system generally consist of a collection of subsystems which has a different function and communicates each other to exchange informations. Recently, a signal transition of a global clock is used to define when the information exchange take place. Synchronization method in exchanging informations using a global clock has arrived to a critical point due to availibility of the technology used. Beside, there are some problems e.g. clock skew, clock distribution, and communication in a high speed synchronous circuit become very hard to handle and costly. There is another problem, an ectromagnetic interference (EMI) which is significant enough to be ignored. So, we need an alternative approach to design digital systems, such as an asynchronous circuit design. <br /> <br /> <br /> Pipelining is an implementation method to increase throughput in which mulptiple instructions are overlapped in execution. Each instruction is divided into some tasks. As long as we have separated resources to execute the tasks, then we can apply the pipeline to execute multiple instructions. <br /> <br /> <br /> The tools for designing and simulating of digital systems that is matured and broadly used by researchers in universities and industries are softwares designed for synchronous digital circuits. It is interresting if we could use the tools that is well supported by existing CAD tool frameworks (that provide simulators, pre-designed modules, mixed-mode simulation, and tools for synthesis, layout and the back annotation of timing information) for design asynchronous digitals systems. <br /> <br /> <br /> In this project, we design asynchronous pipeline employing 2-phase and 4-phase bundled-data push-channel in VHDL. The design has been functionally tested as a standalone, composed as a 5-stages FIFO, and 5-stages pipeline with a functional unit in each stage. Once the design has passed functional testing or simulation, then it is made as a component packed in VHDL package library that can be used as a part of the others desing, such as an asynchronous microprocessor.