#TITLE_ALTERNATIVE#
commonly used now. As asynchronous circuit is clockless, this type of circuit is free from signal distribution problem. Despite having some good point, desingning, modeling, and testing of circuit model should be performed in advance before expecting asynchronous circuit working on <br /> &l...
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| Format: | Final Project |
| Language: | Indonesia |
| Online Access: | https://digilib.itb.ac.id/gdl/view/15579 |
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| Institution: | Institut Teknologi Bandung |
| Language: | Indonesia |
| Summary: | commonly used now. As asynchronous circuit is clockless, this type of circuit is free from signal distribution problem. Despite having some good point, desingning, modeling, and testing of circuit model should be performed in advance before expecting asynchronous circuit working on <br />
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FPGA. That because tool which accompanied FPGA is provided for development of synchronous cicuit. In this research, the designed circuit are registers controllers which works on a clockless processor. the architecture of processor is adapted form an example found in literature. The research is divided into three steps. First step is modelling circuit organisation as petri-net. On the second step, circuit states are inspected for finding paths which create hazard. Functional parts of processor that aren't part of register control modeled as delay. Then additional delay is given to certain path to eliminate hazard. After that, circuit states definition and delay are inspected with discrete time analysis algorithms to verify the circuit behavior. |
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