PERANCANGAN CACHE MEMORY MELALUI PENENTUAN UKURAN BLOK UNTUK MEMINIMALKAN MISS RATE

• Main Author: Heri Setya Budi, Agus
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/3123
• Institution: Institut Teknologi Bandung

Speed of processor has improved more rapidly than speed of memory, therefore this is called as processor memory gap. In order to lesson this gap, a memory hierarchy is used by placing a small size of memory which has high speed so called as cache memory. To improve the performance of cache memory can be conducted by decreasing the miss rate process. Miss rate happened when the CPU needs some data while they are not available in cache memory, so the data should be taken from main memory. The motivation of this research is to enlarge the size of block in cache memory, which is still in its permanent size, so that can maximize principle of locality with assumption that the more data are available the greater probability that can be applied as the reference in the future. It can be prove that the miss rate is progressively reduced by enlarging the measure of the block through the graph does not show linear.