HARDWARE TRO JAN DESIGN AND ITS DETECTION TECHNIQUES USING SIDE CHANNEL ANALYSIS ON CRYPTOGRAPHIC HARDWARE AES IMPLEMENTED ON FPGA

• Main Author: Hanindhito, Bagus
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/39691
• Institution: Institut Teknologi Bandung

Nowaday s, an integrated circuit can have millions or even billio ns of transistors to support its various and complex functi ons which make it more diffi ult and challengin g to desig and manufacture. In the commu nication sy stem, an in tegrated circuit plays an impo rtant role to process and transmi the data between parties who communi ate. Some communic tion device s have abilities to encrypt the data before they are transmitted to make th e communication mo e secret an d more dif ficult to eavesdrop. On the other hand, the involvement of third pa rties during the design and manufact re of an i ntegrated circuit is no t unusual. Third party involvem ent is a problem f or an entit y who wants highly secured communicati on since th ere is a chance th at the com unication devices they use are i mplanted with an evil structure called har dware trojan. The im plantation of hardware trojan i a commu nication device op ens the pos sibilities for the third p arties to eavesdrop th e secret inf rmation transmitted by the device; th us, the se ure communication will not be secret anymore. Because the hardwa re trojan c n come in various fo rm, functi nality, ca ouflage technique s, and injection metho ds, it is difficult to det ct its presence thus be comes a serious co ncern in t he hardware security field. One of the pro mising methods for detecting the presence of hardware trojan is by using the sid e channel analysis, although there are s till a lot f works t o be done to overco me many bstacles associated with it. In this the sis, an inv estigation of hardware trojan behavior and i s detection method will be c onducted. irst, accel erator hard ware used for encrypting the data using Advanced Encryption Standard (AES) is designed and imple mented on a Field Programm able Gate Arrays (F PGA). This encryption acceler ator is one of the hardware blocks from the t h ird party inside an integrated circuit used in communi ation devi es. Then, a hardware trojan capable of leaking AES encryption key is im planted on the acceler ator block. It uses mu tiple output channel i ncluding electromagnetic em anation, inaudible so und waves, ARP and ICMP packets transmitted over ethernet or Wi-Fi, and 802.11 frames transmitted over Wi-Fi. Finally, by using the available measurement and observation instruments mostly available on the lab and easy to obtain, a side channel analysis is performed to detect the presence of the hardware trojan inside the FPGA. By adjusting how the hardware trojan behaves, the effectiveness of the method will be investigated. On the contrary, the technique to design the hardware trojan to avoid detection will also be determined.