PERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION

<b>Abstract</b>: <p align=\"justify\"> <br /> In this thesis, we make a hardware design for multi-precision integers multiplier of 512 bits x 512 bits to perform Montgomery multiplication that repeatedly performed in modular exponentiation, where this modular expon...

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Main Author: Adnan
Format: Theses
Language:Indonesia
Online Access:https://digilib.itb.ac.id/gdl/view/5028
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Institution: Institut Teknologi Bandung
Language: Indonesia
id id-itb.:5028
spelling id-itb.:50282006-03-10T09:53:14ZPERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION Adnan Indonesia Theses INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/5028 <b>Abstract</b>: <p align=\"justify\"> <br /> In this thesis, we make a hardware design for multi-precision integers multiplier of 512 bits x 512 bits to perform Montgomery multiplication that repeatedly performed in modular exponentiation, where this modular exponentiation constitutes main operation in RSA cryptosystem.<p align=\"justify\"> <br /> To improve performance of integer multiplication , we exploit parallelism of standard multiplication algorithm. This lead us to the pipeline architecture comprises eight processing elements that operate at word level to produce partial-product in (carry, sum) form. This design shall accelerate computation of modular exponentiation with modulus p 512 bits and with Chinese remainder theorem; we will be able to get 1024-bit cryptosystem as fast as 512-bit system. Testing both of methods to perform RSA decryption performed with computer program with test vector from RSAES-OAEP Encryption Scheme. text
institution Institut Teknologi Bandung
building Institut Teknologi Bandung Library
continent Asia
country Indonesia
Indonesia
content_provider Institut Teknologi Bandung
collection Digital ITB
language Indonesia
description <b>Abstract</b>: <p align=\"justify\"> <br /> In this thesis, we make a hardware design for multi-precision integers multiplier of 512 bits x 512 bits to perform Montgomery multiplication that repeatedly performed in modular exponentiation, where this modular exponentiation constitutes main operation in RSA cryptosystem.<p align=\"justify\"> <br /> To improve performance of integer multiplication , we exploit parallelism of standard multiplication algorithm. This lead us to the pipeline architecture comprises eight processing elements that operate at word level to produce partial-product in (carry, sum) form. This design shall accelerate computation of modular exponentiation with modulus p 512 bits and with Chinese remainder theorem; we will be able to get 1024-bit cryptosystem as fast as 512-bit system. Testing both of methods to perform RSA decryption performed with computer program with test vector from RSAES-OAEP Encryption Scheme.
format Theses
author Adnan
spellingShingle Adnan
PERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION
author_facet Adnan
author_sort Adnan
title PERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION
title_short PERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION
title_full PERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION
title_fullStr PERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION
title_full_unstemmed PERANCANGAN PENGALI INTEGERMULTI-PRESISI UNTUK SISTEM KRIPTO RSA DENGAN METODA MULTIPLICATION
title_sort perancangan pengali integermulti-presisi untuk sistem kripto rsa dengan metoda multiplication
url https://digilib.itb.ac.id/gdl/view/5028
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