FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD
<b>Abstract:<p align=\"justify\"> <br /> This thesis presents the design of digital fuzzy logic controller (FLC) circuit and its implementation on Complex Programmable Logic Device (CPLD). The FLC circuit is designed in Very-High-Speed Integrated Circuit Hardware Descrip...
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| Format: | Theses |
| Language: | Indonesia |
| Online Access: | https://digilib.itb.ac.id/gdl/view/5244 |
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| Institution: | Institut Teknologi Bandung |
| Language: | Indonesia |
| Summary: | <b>Abstract:<p align=\"justify\"> <br />
This thesis presents the design of digital fuzzy logic controller (FLC) circuit and its implementation on Complex Programmable Logic Device (CPLD). The FLC circuit is designed in Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) model using a design tool, Altera MAX+PLUS II.<p align=\"justify\"> <br />
The thesis proposes the two-input single-output Programmable FLC with parallel architecture. The Programmable FLC can be programmed in terms of its 6 input membership functions, 9 fuzzy implication rules configuration, and its 3 output singleton consequences. Thus this FLC circuit can be applied for wide-range control applications. The FLC circuit is implemented on EPF10K70RC240-4, a FLEX10K CPLD device from Altera containing over 70,000 logic gates.<p align=\"justify\"> <br />
The implementation result shows that it requires 98 % of total logic cells on the device. In-circuit verification shows that the FLC circuit can be operated at clock frequency of 1.573 MHz. Using six-stage datapath pipeline latency, input-output operation delay time is about 3.1786 us. |
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