FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD
<b>Abstract:<p align=\"justify\"> <br /> This thesis presents the design of digital fuzzy logic controller (FLC) circuit and its implementation on Complex Programmable Logic Device (CPLD). The FLC circuit is designed in Very-High-Speed Integrated Circuit Hardware Descrip...
Saved in:
Main Author: | |
---|---|
Format: | Theses |
Language: | Indonesia |
Online Access: | https://digilib.itb.ac.id/gdl/view/5244 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Institut Teknologi Bandung |
Language: | Indonesia |
id |
id-itb.:5244 |
---|---|
spelling |
id-itb.:52442006-08-03T09:55:40ZFUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD Arya Samman, Faizal Indonesia Theses INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/5244 <b>Abstract:<p align=\"justify\"> <br /> This thesis presents the design of digital fuzzy logic controller (FLC) circuit and its implementation on Complex Programmable Logic Device (CPLD). The FLC circuit is designed in Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) model using a design tool, Altera MAX+PLUS II.<p align=\"justify\"> <br /> The thesis proposes the two-input single-output Programmable FLC with parallel architecture. The Programmable FLC can be programmed in terms of its 6 input membership functions, 9 fuzzy implication rules configuration, and its 3 output singleton consequences. Thus this FLC circuit can be applied for wide-range control applications. The FLC circuit is implemented on EPF10K70RC240-4, a FLEX10K CPLD device from Altera containing over 70,000 logic gates.<p align=\"justify\"> <br /> The implementation result shows that it requires 98 % of total logic cells on the device. In-circuit verification shows that the FLC circuit can be operated at clock frequency of 1.573 MHz. Using six-stage datapath pipeline latency, input-output operation delay time is about 3.1786 us. text |
institution |
Institut Teknologi Bandung |
building |
Institut Teknologi Bandung Library |
continent |
Asia |
country |
Indonesia Indonesia |
content_provider |
Institut Teknologi Bandung |
collection |
Digital ITB |
language |
Indonesia |
description |
<b>Abstract:<p align=\"justify\"> <br />
This thesis presents the design of digital fuzzy logic controller (FLC) circuit and its implementation on Complex Programmable Logic Device (CPLD). The FLC circuit is designed in Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) model using a design tool, Altera MAX+PLUS II.<p align=\"justify\"> <br />
The thesis proposes the two-input single-output Programmable FLC with parallel architecture. The Programmable FLC can be programmed in terms of its 6 input membership functions, 9 fuzzy implication rules configuration, and its 3 output singleton consequences. Thus this FLC circuit can be applied for wide-range control applications. The FLC circuit is implemented on EPF10K70RC240-4, a FLEX10K CPLD device from Altera containing over 70,000 logic gates.<p align=\"justify\"> <br />
The implementation result shows that it requires 98 % of total logic cells on the device. In-circuit verification shows that the FLC circuit can be operated at clock frequency of 1.573 MHz. Using six-stage datapath pipeline latency, input-output operation delay time is about 3.1786 us. |
format |
Theses |
author |
Arya Samman, Faizal |
spellingShingle |
Arya Samman, Faizal FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD |
author_facet |
Arya Samman, Faizal |
author_sort |
Arya Samman, Faizal |
title |
FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD |
title_short |
FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD |
title_full |
FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD |
title_fullStr |
FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD |
title_full_unstemmed |
FUZZY LOGIC CONTROLLER CIRCUIT DESIGN AND ITS IMPLEMENTATION ON CPLD |
title_sort |
fuzzy logic controller circuit design and its implementation on cpld |
url |
https://digilib.itb.ac.id/gdl/view/5244 |
_version_ |
1820663631841329152 |