DESIGN AND IMPLEMENTATION OF SIMULATOR FOR RISC-V LEARNING SYSTEM
The development of computers, one of which is RISC-V ISA, is accompanied by the increasing need for learning tools. One of the important tools to learn RISC-V is a simulator. Simulators can help students become familiar with a set of computer architectures, especially RISC-V instructions. That is...
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| Format: | Final Project |
| Language: | Indonesia |
| Online Access: | https://digilib.itb.ac.id/gdl/view/66867 |
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| Institution: | Institut Teknologi Bandung |
| Language: | Indonesia |
| Summary: | The development of computers, one of which is RISC-V ISA, is accompanied by the
increasing need for learning tools. One of the important tools to learn RISC-V is a
simulator. Simulators can help students become familiar with a set of computer
architectures, especially RISC-V instructions. That is why simulators can facilitate
student learning and enhance the experience of computer architecture.
The design and implementation of the simulator consist of a text editor, an
interpreter to binary, and a register simulation. This simulator allows user-supplied
RISC-V assembly source code to run on a single-cycle processor, making it easy to
follow the instruction flow when viewing register and memory data. The
implementation of the binary translator subsystem also allows users to convert
assembly to binary code for easy integration with other learning modules such as
RTL implementations. Tests that have been carried out on the system
implementation show the simulator's ability to run 32 RISC-V-based instructions
and have been compared with the processor implementation using Verilog |
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