RISC-V processor FPGA implementation

• Main Author: Tey, Jing Kai
• Other Authors: Vun Chan Hua, Nicholas
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Computer and Information Science; Engineering; FPGA; RISC-V; RV32I; Microprocessor
• Online Access: https://hdl.handle.net/10356/181173
• Institution: Nanyang Technological University

RISC-V is an open-standard Instruction Set Architecture (ISA), and RV32I is a subset of RISC-V instructions. The simplicity of RV32I makes it ideal for educational purposes. This project is to implement a RISC-V (RV32I) Processor (softcore with a simple Harvard architecture) on Nexys A7 Xilinx A...