RISC-V processor FPGA implementation

• Main Author: Tey, Jing Kai
• Other Authors: Vun Chan Hua, Nicholas
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Computer and Information Science; Engineering; FPGA; RISC-V; RV32I; Microprocessor
• Online Access: https://hdl.handle.net/10356/181173
• Institution: Nanyang Technological University

RISC-V is an open-standard Instruction Set Architecture (ISA), and RV32I is a subset of RISC-V instructions. The simplicity of RV32I makes it ideal for educational purposes. This project is to implement a RISC-V (RV32I) Processor (softcore with a simple Harvard architecture) on Nexys A7 Xilinx Artix®-7 FPGA using Verilog. Different processor micro-architectures, single-cycle, multi-cycle and multi-stage pipeline (with static branch predictor) are explored in this project. The design is based on Hardware Description Languages (HDL) - Verilog and IDE - Vivado Design Suite. In addition to the RV32I processor, essential modules such as universal asynchronous receiver/transmitter (UART Tx and Rx), seven-segment display, and other device modules were developed. A basic loader firmware in C was also developed to provide the capability to load custom user programs and provide software access to the mapped devices. The complete implementation of RV32I on Nexys A7 FPGA board offers valuable insight into computer architectures, integrating different knowledge across the years into a comprehensive understanding.