PATH PLANNING MODELING AND ARCHITECTURE DESIGN FOR Q-LEARNING ALGORITHM USING FPGA

• Main Author: Fakhrudin, Muhammad
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/71635
• Institution: Institut Teknologi Bandung

The development of artificial intelligence is currently growing rapidly in many scientific sectors. One of the cases is the path-planning process which requires a specific algorithm to find the optimal route. The use of AI algorithms in the process of finding the shortest path will involve a lot of data so that it takes time in the computation process. This research aims to accelerate the architectural design of the route planning process using the q-learning algorithm with the shortest path results and reach convergence. The acceleration is carried out by implementing the RTL architectural design on the FPGA board to speed up the computational process of processing data which was previously done by simulating the RTL model and architecture in the software. Based on the path planning system model results, the percentage of agent success in reaching the destination is 58.8% and 63.5% in the RTL architectural design. The simulation time obtained in the software requires 0,2248 seconds and 0.0003 seconds for the implementation of the RTL architecture with an output clock frequency of 40 MHz and results in an accelerator acceleration of 731.72 times faster.