CONTROL UNIT, LOAD STORE UNIT, AND ARITHMETIC LOGICAL UNIT DESIGN FOR IMPLEMENTING RISC – V BASED SOFT CORE PROCESSOR ON FPGA

• Main Author: Dwiputra, Yansen
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/82255
• Institution: Institut Teknologi Bandung

The use of microprocessors has become commonplace for executing digital processes, especially in hardware devices such as System on Chip (SoC) and microcontrollers. The utilization of microprocessors is costly for both research and industrial purposes due to licensing and intellectual property (IP) regulations, making further development and modification of these microprocessors challenging and expensive. Therefore, a microprocessor that addresses licensing costs and ease of modification is required. One viable solution is to use open-source and license-free microprocessors such as RISC-V and its derivatives. One of the RISC-V derivatives that has been developed is NEORV32, a RISC-V-based microprocessor with a 2-stage pipeline. Using NEORV32 can mitigate the issues related to modification difficulties and high licensing costs associated with microprocessors like ARM. Thus, before implementing NEORV32, it is necessary to validate its functionality and features to ensure the performance of the components within NEORV32. Testing of the NEORV32 components was conducted on three crucial components: the Arithmetic Logical Unit (ALU), Load Store Unit (LSU), and Control Unit (CU). The tests on these three components demonstrated functional success and the features provided by NEORV32. Therefore, it can be concluded that the functionality of these three components is reliable and can be integrated with other components.