FPGA BASED HARDWARE ACCELERATOR DESIGN OF A* ALGORITHM FOR GRID PATH PLANNING IN MOBILE ROBOT

• Main Author: Daffa Rasyid, Muhammad
• Format: Final Project
• Language: Indonesia
• Subjects: Teknik (Rekayasa, enjinering dan kegiatan berkaitan)
• Online Access: https://digilib.itb.ac.id/gdl/view/82460
• Institution: Institut Teknologi Bandung

Efficient inventory management is crucial for ensuring smooth warehouse operations by verifying stock accuracy, particularly in the Fast-Moving Consumer Goods (FMCG) industry such as at KKP ITB. The accuracy and time efficiency in the inventory process significantly impact warehouse operations and management. Accurate inventory ensures that the recorded stock matches the physical stock in the warehouse, preventing stock shortages or excesses that can lead to financial losses and missed sales opportunities. Meanwhile, time efficiency in inventory minimizes operational disruptions and allows for faster stock turnover. Accuracy and efficiency in inventory can be improved through automation, making the inventory process more concrete and avoiding human errors. To achieve high accuracy and efficiency, an autonomous mobile robot was developed to perform inventory processes using barcode scanning to count items. This robot navigates autonomously during inventory using a grid map generated by lidar area mapping. During its movement, the robot performs path planning to find the fastest route, ensuring efficient inventory time. This final project discusses the development of an FPGA-based hardware accelerator using the A* algorithm to compute path planning on a grid map for the mobile robot. The A* algorithm is chosen for its ability to find the optimal path by integrating Dijkstra’s algorithm and greedy best-first search (GBFS). The A* algorithm is developed by utilizing the parallel computing capabilities of the FPGA-based hardware accelerator, surpassing the serial computing capabilities of software alone. Key aspects of this development include a configurable grid map model to adapt to dynamic map conditions, efficient architecture to minimize the use of FPGA logic component resources, and precise heuristic calculations to ensure optimal path generation. Development results indicate that the FPGA-based hardware accelerator enhances computation speed by 30 times compared to C++ software and 100 times compared to Python software.