DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX

Leon2 processor has a hardware debug support module as communication media with host computer. Host computer is an external monitor for Leon2 processor. With this feature Leon2 processor can be applied for embedded system, for examples Automated Teller Machine, Automated Ticketing Machine, Vending M...

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Main Author:	ABDUL RAHMAN (NIM 23205023), SUTISNA
Format:	Theses
Language:	Indonesia
Online Access:	https://digilib.itb.ac.id/gdl/view/9414
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Institution:	Institut Teknologi Bandung
Language:	Indonesia

id	id-itb.:9414
spelling	id-itb.:94142017-09-27T15:37:36ZDESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX ABDUL RAHMAN (NIM 23205023), SUTISNA Indonesia Theses INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/9414 Leon2 processor has a hardware debug support module as communication media with host computer. Host computer is an external monitor for Leon2 processor. With this feature Leon2 processor can be applied for embedded system, for examples Automated Teller Machine, Automated Ticketing Machine, Vending Machine, etc. Its required an additional modules thus the running application not only can be displayed on host computer monitor but also on dedicated monitor which connected with Leon2 processor. This research presents the designing of graphics interface module for Leon2 processor with release Leon2-1.0.32-xst and text editor system as testbench. <br /> <br /> <br /> <br /> <br /> <br /> Design process is started by determining a specification. Then continued with graphics interface modules design in RTL description form with VHDL language. Next step is performed functional simulation process using ModelSim and Quartus II 6.1. Simulation process started with simulation task for modules in system then continued with integrated system simulation. A text editor system is implemented on FPGA by using Altera APEX20KE development board. In this process, an implemented system has been working to receive text data from keyboard and displayed its in monitor. Based on implementation task result, total logic elements used is 9.281/ 16.640 (56%). System maximum frequency reached is 26.73 MHz. <br /> text
institution	Institut Teknologi Bandung
building	Institut Teknologi Bandung Library
continent	Asia
country	Indonesia Indonesia
content_provider	Institut Teknologi Bandung
collection	Digital ITB
language	Indonesia
description	Leon2 processor has a hardware debug support module as communication media with host computer. Host computer is an external monitor for Leon2 processor. With this feature Leon2 processor can be applied for embedded system, for examples Automated Teller Machine, Automated Ticketing Machine, Vending Machine, etc. Its required an additional modules thus the running application not only can be displayed on host computer monitor but also on dedicated monitor which connected with Leon2 processor. This research presents the designing of graphics interface module for Leon2 processor with release Leon2-1.0.32-xst and text editor system as testbench. <br /> <br /> <br /> <br /> <br /> <br /> Design process is started by determining a specification. Then continued with graphics interface modules design in RTL description form with VHDL language. Next step is performed functional simulation process using ModelSim and Quartus II 6.1. Simulation process started with simulation task for modules in system then continued with integrated system simulation. A text editor system is implemented on FPGA by using Altera APEX20KE development board. In this process, an implemented system has been working to receive text data from keyboard and displayed its in monitor. Based on implementation task result, total logic elements used is 9.281/ 16.640 (56%). System maximum frequency reached is 26.73 MHz. <br />
format	Theses
author	ABDUL RAHMAN (NIM 23205023), SUTISNA
spellingShingle	ABDUL RAHMAN (NIM 23205023), SUTISNA DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX
author_facet	ABDUL RAHMAN (NIM 23205023), SUTISNA
author_sort	ABDUL RAHMAN (NIM 23205023), SUTISNA
title	DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX
title_short	DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX
title_full	DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX
title_fullStr	DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX
title_full_unstemmed	DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX
title_sort	design and implementation graphics interface module for leon2 processor in fpga altera apex
url	https://digilib.itb.ac.id/gdl/view/9414
_version_	1820664689194958848

DESIGN AND IMPLEMENTATION GRAPHICS INTERFACE MODULE FOR LEON2 PROCESSOR IN FPGA ALTERA APEX

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