Design of a 7-Stage pipeline RISC processor (MEM STAGE)

• Main Author: Choo, Jia Zheng
• Format: Final Year Project / Dissertation / Thesis
• Published: 2022
• Subjects: TA Engineering (General). Civil engineering (General); TF Railroad engineering and operation; TG Bridge engineering; TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utar.edu.my/4625/1/fyp_CT_2022_CJZ.pdf; http://eprints.utar.edu.my/4625/
• Institution: Universiti Tunku Abdul Rahman

This project is about the design and implementation of a 32-bits RISC 7-Stage pipeline processor for academic purpose. The main objective of this project is to improve the performance of the existing 32-bits RISC 5-stage pipeline processor developed in Faculty of Information, Communication and Techn...