Design of a 7-Stage pipeline RISC processor (MEM STAGE)

• Main Author: Choo, Jia Zheng
• Format: Final Year Project / Dissertation / Thesis
• Published: 2022
• Subjects: TA Engineering (General). Civil engineering (General); TF Railroad engineering and operation; TG Bridge engineering; TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utar.edu.my/4625/1/fyp_CT_2022_CJZ.pdf; http://eprints.utar.edu.my/4625/
• Institution: Universiti Tunku Abdul Rahman

This project is about the design and implementation of a 32-bits RISC 7-Stage pipeline processor for academic purpose. The main objective of this project is to improve the performance of the existing 32-bits RISC 5-stage pipeline processor developed in Faculty of Information, Communication and Technology, University Tunku Abdul Rahman. The performance of the processor is improved and optimized by increasing the number of pipeline stages to obtain a shorter time delay for each stage. The MEM stages of the existing pipeline processor contribute to the longest timing delay, which reduce the performance of the processor due to the imbalance logics among the stages. In this project, the data cache unit is decomposed and pipelined into 2 stages. Cache unit access will now require two clock cycle if a CACHE HIT is detected. Another extra stage is reserved for the implementation of Translation Look Aside Buffer (TLB) in the future. Some modifications on the cache controller is done to improve its performance too. The newly developed data cache unit is modelled using Verilog coding follow with its functional verification. Lastly, synthesis and implementation using Xilinx Vivado is done to obtain the timing delay of the new developed 7-stage RISC pipeline processor.