HCI degradation effect on VDMOS transistor with geometric and process variations

• Main Authors: Yusof, H.H.M., Soin, N., Murti, W.B.
• Format: Article
• Published: Research India Publications 2015
• Subjects: TA Engineering (General). Civil engineering (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.um.edu.my/19329/; https://www.ripublication.com/Volume/ijaerv10n19.htm
• Institution: Universiti Malaya

In high power systems, the application of transistor has significantly increased and this includes the important of VDMOS type of transistor. However, reliability issues have always been addressed in high voltage and current operated applications. In order to counter this issues, various studies and analysis have been carried out till today. One of the well-known critical issue is known as Hot Carrier Injection (HCI). HCI happens due to high electrical field between source and drain of transistor. Therefore, several process parameters need to be understood before designing a transistor. Therefore, this paper aims to analyze HCI effect on the parameters of the transistor fabrication process which includes the geometric and process variations. In order to meet the objective, a high voltage VDMOS structure has been virtually fabricated in this work. This work results in a relationship among doping concentration, transistor material characteristics and geometrical variation.