A new switched capacitor 7L inverter with triple voltage gain and low voltage stress
In this brief, a new switched capacitor based multilevel inverter topology is proposed. The proposed topology generates seven level (7L) output voltage using a single dc voltage source along with two floating capacitors. The output voltage of the proposed topology is three-times higher than the inpu...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Published: |
IEEE-Inst Electrical Electronics Engineers Inc
2020
|
| Subjects: | |
| Online Access: | http://eprints.um.edu.my/36595/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Universiti Malaya |