Analysis of reliability for fault tolerant design in NANO CMOS logic circuit
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Universiti Malaysia Perlis (UniMAP)
2017
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my.unimap-499452017-11-21T01:13:38Z Analysis of reliability for fault tolerant design in NANO CMOS logic circuit Manimekalai, D. Pradipkumar, D. manimekalai7@gmail.com Nano CMOS Fault Reliability Link to publisher's homepage at http://ijneam.unimap.edu.my/ The emerging nano scaled electronic devices are Carbon Nanotubes (CNT), Silicon nanowires (SINW), nano CMOS switches, etc. In Nano CMOS switches, the devices can be interconnected to build the nano scaled CMOS circuit.In this nano CMOS circuit,faults occur at three levels, such as gate level,circuit level and switch level. This paper focusses on the switch level faults of stuck-open or stuck-off and stuck-short or stuck-on that frequently occurs in CMOS switches. To overcome the switch level faults and to increase the reliability, the fault tolerant technique known as the Quadded Transistor (QT) structure is used. An analytical model has been formulated to determine the probability of failure by analyzing the stuck open and stuck short faults. Also, the model has been formulated by implementing QT structure for the single CMOS NAND2 gate. By the use of analytical formulations,the results has been simulated for the occurrence of minimum to maximum number of defective transistors in CMOS logic circuit 2017-10-12T04:08:57Z 2017-10-12T04:08:57Z 2017 Article International Journal of Nanoelectronics and Materials, vol.10 (2), 2017, pages 123-138 1985-5761 (Printed) 1997-4434 (Online) http://dspace.unimap.edu.my:80/xmlui/handle/123456789/49945 en Universiti Malaysia Perlis (UniMAP) |
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UniMAP Library |
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Malaysia |
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Universiti Malaysia Perlis |
| content_source |
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http://dspace.unimap.edu.my/ |
| language |
English |
| topic |
Nano CMOS Fault Reliability |
| spellingShingle |
Nano CMOS Fault Reliability Manimekalai, D. Pradipkumar, D. Analysis of reliability for fault tolerant design in NANO CMOS logic circuit |
| description |
Link to publisher's homepage at http://ijneam.unimap.edu.my/ |
| author2 |
manimekalai7@gmail.com |
| author_facet |
manimekalai7@gmail.com Manimekalai, D. Pradipkumar, D. |
| format |
Article |
| author |
Manimekalai, D. Pradipkumar, D. |
| author_sort |
Manimekalai, D. |
| title |
Analysis of reliability for fault tolerant design in NANO CMOS logic circuit |
| title_short |
Analysis of reliability for fault tolerant design in NANO CMOS logic circuit |
| title_full |
Analysis of reliability for fault tolerant design in NANO CMOS logic circuit |
| title_fullStr |
Analysis of reliability for fault tolerant design in NANO CMOS logic circuit |
| title_full_unstemmed |
Analysis of reliability for fault tolerant design in NANO CMOS logic circuit |
| title_sort |
analysis of reliability for fault tolerant design in nano cmos logic circuit |
| publisher |
Universiti Malaysia Perlis (UniMAP) |
| publishDate |
2017 |
| url |
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/49945 |
| _version_ |
1643802829411844096 |