FSM based green memory design and its implementation on ultrascale plus FPGA
In this work, we are going to design a memory using Verilog programming in Vivado 2018.3 Integrated Development Environment and implement it on Kintex UltraScale+ FPGA. In order to make it green, we are reducing power dissipation of our design using power supply settings of UltraScale FPGA that supp...
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| Main Authors: | , , , , |
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| Format: | Article |
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Innovare Academics Sciences Pvt. Ltd
2023
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| Institution: | Universiti Tenaga Nasional |
| Summary: | In this work, we are going to design a memory using Verilog programming in Vivado 2018.3 Integrated Development Environment and implement it on Kintex UltraScale+ FPGA. In order to make it green, we are reducing power dissipation of our design using power supply settings of UltraScale FPGA that support a dual-voltage operation of the primary core fabric. Operating Voltage (VCCINT) of 7 Series (28nm) VNOM, UltraScale (20nm) VNOM, UltraScale+ (16nm) VNOM, and UltraScale+ (16nm) VLOW are 1V, 0.95V, 0.85V, and 0.72V respectively. In our work, we are 0.873 V operating voltage and compare its power dissipation with power dissipation by 0.9V and 0.928 V operating voltage. There is 2.87-6.42 % reduction in power dissipation when we scale down supply voltage from 0.928 V to 0.873 V. � 2020 Innovare Academics Sciences Pvt. Ltd. All rights reserved. |
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