Scaling down of the 32 nm to 22 nm gate length NMOS transistor

• Main Authors: Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.
• Other Authors: 36570222300
• Format: Conference paper
• Published: 2023
• Subjects: high-k/metal gate; Scaling down ratio; Silvaco; Leakage currents; Silicides; Tungsten; Design and simulation; Design simulations; Down-scaling; Electrical characterization; Fabrication tool; Gate length; Metal gate; NMOS transistors; Optimal values; Scale down; Scaling down; TiO; Tungsten silicide; Titanium dioxide
• Institution: Universiti Tenaga Nasional

In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate in...