Process parameters optimization of 14nm p-type MOSFET using 2-D analytical modeling
Simulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is conferred in this paper. The device is scaled down from a 32nm transistor which is from the former research. A combination of insulator-conductor that were used includes a high-k material and a metal gate w...
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| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | en_US |
| Published: |
2017
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| Institution: | Universiti Tenaga Nasional |
| Language: | en_US |