Numerical study of side gate junction-less transistor in on state

Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in...

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Main Authors: Dehzangi, Arash, Larki, Farhad, Yeop Majlis, Burhanuddin, Hamidon, Mohd Nizar, Navasery, Manizheh, Gharibshahi, Elham, Khalilzadeh, Nasrin, Vakilian, Mohammadmahdi, Saion, Elias
Format: Conference or Workshop Item
Language:English
Published: IEEE 2013
Online Access:http://psasir.upm.edu.my/id/eprint/68136/1/Numerical%20study%20of%20side%20gate%20junction-less%20transistor%20in%20on%20state.pdf
http://psasir.upm.edu.my/id/eprint/68136/
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Institution: Universiti Putra Malaysia
Language: English
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spelling my.upm.eprints.681362019-05-09T01:42:35Z http://psasir.upm.edu.my/id/eprint/68136/ Numerical study of side gate junction-less transistor in on state Dehzangi, Arash Larki, Farhad Yeop Majlis, Burhanuddin Hamidon, Mohd Nizar Navasery, Manizheh Gharibshahi, Elham Khalilzadeh, Nasrin Vakilian, Mohammadmahdi Saion, Elias Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of V DS and V G on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain. IEEE 2013 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/68136/1/Numerical%20study%20of%20side%20gate%20junction-less%20transistor%20in%20on%20state.pdf Dehzangi, Arash and Larki, Farhad and Yeop Majlis, Burhanuddin and Hamidon, Mohd Nizar and Navasery, Manizheh and Gharibshahi, Elham and Khalilzadeh, Nasrin and Vakilian, Mohammadmahdi and Saion, Elias (2013) Numerical study of side gate junction-less transistor in on state. In: 2013 IEEE Regional Symposium on Micro and Nano Electronics (RSM 2013), 25-27 Sept. 2013, Langkawi, Kedah, Malaysia. (pp. 398-401). 10.1109/RSM.2013.6706575
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of V DS and V G on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain.
format Conference or Workshop Item
author Dehzangi, Arash
Larki, Farhad
Yeop Majlis, Burhanuddin
Hamidon, Mohd Nizar
Navasery, Manizheh
Gharibshahi, Elham
Khalilzadeh, Nasrin
Vakilian, Mohammadmahdi
Saion, Elias
spellingShingle Dehzangi, Arash
Larki, Farhad
Yeop Majlis, Burhanuddin
Hamidon, Mohd Nizar
Navasery, Manizheh
Gharibshahi, Elham
Khalilzadeh, Nasrin
Vakilian, Mohammadmahdi
Saion, Elias
Numerical study of side gate junction-less transistor in on state
author_facet Dehzangi, Arash
Larki, Farhad
Yeop Majlis, Burhanuddin
Hamidon, Mohd Nizar
Navasery, Manizheh
Gharibshahi, Elham
Khalilzadeh, Nasrin
Vakilian, Mohammadmahdi
Saion, Elias
author_sort Dehzangi, Arash
title Numerical study of side gate junction-less transistor in on state
title_short Numerical study of side gate junction-less transistor in on state
title_full Numerical study of side gate junction-less transistor in on state
title_fullStr Numerical study of side gate junction-less transistor in on state
title_full_unstemmed Numerical study of side gate junction-less transistor in on state
title_sort numerical study of side gate junction-less transistor in on state
publisher IEEE
publishDate 2013
url http://psasir.upm.edu.my/id/eprint/68136/1/Numerical%20study%20of%20side%20gate%20junction-less%20transistor%20in%20on%20state.pdf
http://psasir.upm.edu.my/id/eprint/68136/
_version_ 1643839111916683264